Mobile and portable electronics have advanced rapidly and there is an increasing demand for high performance and low power digital circuits. The main technology approach for reducing power has been power supply scaling. Power supply scaling generally needs to be accompanied by threshold voltage reduction in order to preserve low Vt device performance. Unfortunately, low Vt tends to raise sub-threshold leakage.
One solution has been to tie the gate of a semiconductor device to the device's substrate so as to operate the device as a dynamic threshold voltage MOSFET (DTMOS). This is illustrated as a plan view in FIG. 1A and a schematic diagram in FIG. 1B. Illustrated is a gate pedestal 11 flanked by source 13 and drain 14. P+ connector 12 makes a hard connection between the gate 11 and the base 15. In this configuration, the gate input voltage forward biases the substrate/source junction and causes Vth to decrease. However, the gate voltage of a DTMOS should be limited to approximately one diode voltage (e.g., −0.7 V at room temperature) to avoid significant junction leakage.
The present disclosure discloses a solution to this problem that allows a MOS device to operate under power supply voltages larger than 0.7 V.